Chapter 6: Digitally Controlled Frequency Synthesizers : PLLs

example 6.1, Page No. 247

In [9]:
# PLL circuit parameters(refere fig. 6.13)

import math
#Variable declaration
Ct = 0.005 *10**-6                 # external capacitor for VCO
Rt = 10*10**3                      # external resistance for VCO
V = 20.0                           # supply voltage(V_positive - V_negative) 
C = 10*10**-6                      # capacitance

#Calculations
#(i)
fout = 0.25/(Rt*Ct)

#(ii)
fL = 8*fout/V

#(iii)
fC = fL/(2*math.pi*3.6*10**3*C)
fC = math.sqrt(fC)

#in kHz
fout = fout/10**3
fL = fL/10**3

#Result
print("(i)free running frequency, fout = %.0fkHz\n(ii)Lock range, fL = +/-%.0f kHz\n(iii)Calpture range, fC = +/-%d Hz"%(fout,fL,fC))

(i)free running frequency, fout = 5kHz
(ii)Lock range, fL = +/-2 kHz
(iii)Calpture range, fC = +/-94 kHz

example 6.2, Page No. 254

In [13]:
# Digital frequency synthesizer

import math
#Variable declaration
R = 4                # resolution of digital frequency synthesizer
Fm = 200*10**3       # maximum frequency output

#Calculations
fclk = Fm*2.2
k = fclk/R
n = math.log(k)/math.log(2)

#Result
print("frequency of reference oscillator = %.0f kHz\nno of bits required = %.0f"%(fclk/1000,math.ceil(n)))

frequency of reference oscillator = 440 kHz
no of bits required = 17