# CHAPTER 3- 8085 MICROPROCESSOR ARCHITECHTURE AND MEMORY INTERFACING¶

## Example 3.2- Pg no. 78¶

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##page no 78
##example no 3.2
##EXECUTING THE INSTRUCTION.
A=82# ##contents of the accumulator.
print ('Accumulator= ')#
print (A)#
TR=A# ##contents of the accumulator tranferred to the temporary register.
print ('Temporary Register= ')#
print (TR)#
C=TR# ##contents of the temporary register are transferred to register C.
print ('Register C= ')#
print (C)#

Accumulator=
82
Temporary Register=
82
Register C=
82


## Example 3.3- Pg no.82¶

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##page no 82
##example no 3.3
##TIME REQUIRED FOR EXECUTION.
A=32# ## MVI A,32H loads the value 32 in accumulator.
print  '%s' %('Accumulator= ')#
print  '%s' %(A)#
##calculating the execution time for instruction.
f=2# ## clock frequncy.
print '%s %.6f %s' % ('clock frequency= ',f,' MHz \n')#
t=1./f# ## T-state=clock period
print '%s %.6f %s' % ('T-state=clock period= ',t,' microsec \n')#
t1=4.*t# ## execution time for opcode fetch.
print '%s %.6f %s' % ('Execution time for opcode fetch= ',t1,' microsec \n')#
t2=3.*t# ## execution time for memory read.
print '%s %.6f %s' % ('Execution time for memory read= ',t2,' microsec \n')#
t3=7.*t# ## execution time for instruction.
print '%s %.6f %s' % ('Execution time for instruction= ',t3,' microsec \n')#

Accumulator=
32
clock frequency=  2.000000  MHz

T-state=clock period=  0.500000  microsec

Execution time for opcode fetch=  2.000000  microsec

Execution time for memory read=  1.500000  microsec

Execution time for instruction=  3.500000  microsec



## Example 3.5 - Pg no. 91¶

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####page no 91
##example no 3.5
print ('A10-A0 are  address lines for register select. \n')#
print ('A15-A11 are address lines for chip select. \n \n')#
print ('A15 A14 A13 A12 A11 \n')#
print (' 1  0   0   0   1 \n \n')# ##chip select bits have to be active low always to select that chip.
print ('A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 \n')#
print ('0   0  0  0  0  0  0  0  0  0  0  \n')# ##this selects the register
print ('The above combination selects the memory address 8800H. \n \n')#
print ('A15 A14 A13 A12 A11 \n')#
print (' 1  0   0   0   1 \n \n')# ##chip select bits have to be active low always to select that chip.
print ('A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 \n')#
print ('1   1  1  1  1  1  1  1  1  1  1  \n')# ##this selects the register
print ('The above combination selects the memory address 88FFH. \n \n')#
##thus this chip can select any memory location from 8800H to 88FFH.

A10-A0 are  address lines for register select.

A15-A11 are address lines for chip select.

A15 A14 A13 A12 A11

1  0   0   0   1

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0   0  0  0  0  0  0  0  0  0  0

The above combination selects the memory address 8800H.

A15 A14 A13 A12 A11

1  0   0   0   1

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1   1  1  1  1  1  1  1  1  1  1

The above combination selects the memory address 88FFH.



## Example 3.6 - Pg no. 95¶

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####page no 95
##example no 3.6
print ('A7-A0 are address lines for register select. \n')#
print ('A10-A8 address lines are dont care conditions. \n')#
print ('A15-A11 are address lines for chip select. \n \n')#
print ('A15 A14 A13 A12 A11 \n')#
print (' 0  0   1   0   0 \n \n')# ##chip select bits have to be active low always to select that chip.
print ('A10 A9 A8 \n')#
print ('0  0  1  \n \n')# ##this is the don't care condition.
print ('A7 A6 A5 A4 A3 A2 A1 A0 \n')#
print ('0  0  0  0  0  0  0  0  \n')# ##this selects the register
print ('The above combination selects the memory address 2100H. \n \n')#
print ('A15 A14 A13 A12 A11 \n')#
print (' 0  0   1   0   0 \n \n')# ##chip select bits have to be active low always to select that chip.
print ('A10 A9 A8 \n')#
print ('0  0  1  \n \n')# ##this is the don't care condition.
print ('A7 A6 A5 A4 A3 A2 A1 A0 \n')#
print ('1  1  1  1  1  1  1  1  \n')# ##this selects the register
print ('The above combination selects the memory address 21FFH. \n \n')#
##thus this chip can select any memory location from 2100H to 21FFH.

A7-A0 are address lines for register select.

A10-A8 address lines are dont care conditions.

A15-A11 are address lines for chip select.

A15 A14 A13 A12 A11

0  0   1   0   0

A10 A9 A8

0  0  1

A7 A6 A5 A4 A3 A2 A1 A0

0  0  0  0  0  0  0  0

The above combination selects the memory address 2100H.

A15 A14 A13 A12 A11

0  0   1   0   0

A10 A9 A8

0  0  1

A7 A6 A5 A4 A3 A2 A1 A0

1  1  1  1  1  1  1  1

The above combination selects the memory address 21FFH.


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